Azcom highly experienced team offers FPGA design services across all the major device families. Covering the complete development process, from architecture definition to RTL code development, simulation and testing, we support customers to solve their design challenges in different application domains.
We have major experience in signal processing, complex DFEs design and 5G RU FPGA firmware development.
- FPGA design services on major FPGA device families (Xilinx, Intel and Lattice).
- Full development process ranging from architecture definition to RTL code development, simulation and testing
- Customer guidance in FPGA device selection
- High speed interface implementation and last generation high complexity IP integration
- Finite precision processing simulation fully aligned with RTL FPGA code implementation
- Design migration to latest devices
- ASIC to FPGA conversion for device prototyping and cost effective early design validation
- Adoption of new technologies such as the Xilinx Zynq®-7000 and Intel SoCs (Programmable SoC) to reduce time to market
- Design experience involving multiple clocks domains and high frequency architectures
- Solving congested logic load designs issues in term of timing constraints and best logic cells allocations
- High performance designs based on large degree of parallelism and pipelining
- Optimized digital processing architecture mapping for high complexity algorithm implementation
- MATLAB finite precision processing chain and simulation to shorten development time, enabling early performance evaluation and enforcing solution validation
Azcom engineering team has consolidated expertise in signal processing domain, complex DFEs design and O-RAN 5G RU development. These systems make extensive use of FPGA technology to accelerate performance demanding functional blocks, on which Azcom has a consolidated implementation experience.
Some key examples are:
- O-RAN 5G RU – Low PHY, CPRI, eCPRI, U/C plane function, eCPRI M/S plane and O&M on SoC FPGA processor cores.
- Radio Digital Up and Down conversion chains (interpolators & decimators, shaping filters, CFR, FFT/IFFT, NCO/CORDIC, digital modulation/demodulation)
- Coding/decoding (block, convolutional Viterbi and Turbo)
- Channel equalization
- Latest generation power amplifier Digital Pre-distortion algorithms
- Matrices manipulations (pseudoinverse, least squares, linear system solver, Cholesky, QR decomposition)
- Fixed-point precision adaptation strategy on FPGA
O-RAN 5G RU – Low PHY, CPRI, eCPRI, U/C plane function, eCPRI M/S plane and O&M on SoC FPGA processor cores.
Radio Digital Up and Down conversion chains (interpolators & decimators, shaping filters, CFR, FFT/IFFT, NCO/CORDIC, digital modulation/demodulation)
Coding/decoding (block, convolutional Viterbi and Turbo)
Latest generation power amplifier Digital Pre-distortion algorithms
Matrices manipulations (pseudoinverse, least squares, linear system solver, Cholesky, QR decomposition)
Fixed-point precision adaptation strategy on FPGA
4G UE PHY stack
4G Multi UE Physical Layer stack for an LTE macro cell testing simulator; implemented on a Xilinx Kintex Ultrascale FPGA.
5G RU DFE Conversion Chains
5G TX/RX multi band/carrier/antenna Digital Up/Down conversion chains offering high configuration flexibility in terms of instantaneous bandwidth and frequency allocation for each antenna beam; implemented on Xilinx Zynq U+ FPGA.
4G/5G O-Ran 7.2 Low-Phy Offload
Complete 4G/5G Oran 7.2 Low-Phy Offload processing on Xilinx Zynq U+ FPGA, supporting a wide bandwidth range from 1.4MHz up to 100MHz, a flexible fully configurable subcarrier spacing and slot length, and a high number of layers/beams management, including a fully optimized configurable FFT/IFFT engine pool.
Multi-Antenna/Carriers/Bands Crest Factor Reduction
Fully configurable Crest Factor Reduction functional block for a massive MIMO RRH, supporting multiple stage iterative cancellation and high flexibility on antennas, carriers and bandwidth configuration; implemented on Xilinx Zynq U+ and Xilinx Kintex Ultrascale +
L1 BaseBand Modulation/Demodulation Chains
Complete L1 BaseBand modulation/demodulation chains and high performance, high sensitivity receiver, based on LSE channel estimation and MMSE equalization; implemented on a pool of Xilinx Kintex Ultrascale FPGAs.
High Performance MMSE Digital Predistortion Algorithms
High performance multi carriers/bands MMSE Digital Predistortion Algorithms for a macro RRH, suitable for latest generation high power amplifiers, supporting high sample rate and a large armonic range predistortion capability; implemented on Xilinx FPGA.
Multi standard flexible CPRI antenna I/F
High rate CPRI antenna interface functional block, suitable for both Master (Baseband) and Slave (RRH) endpoints, with a high configuration flexibility to match with different wireless standards (3G/4G), bandwidths, samples resolutions, number of antenna/carriers; available for a wide range of Xilinx FPGA devices.
As part of Xilinx Partner Program, Azcom assists system designers to perform a rapid integration of Xilinx FPGAs, SoCs, 3DICs, intellectual property, and software defined solutions.
Our engineering team alliance with privileged technical support and exclusive access to new technologies, help us boost cutting-edge solutions exploiting top FPGA options.
Moreover, Azcom has been selected to support the Xilinx T1 Telco Accelerator card for 5G ODU an VBBU market and have access to last generation devices preview, such as last generation RFSoC gen3.